Since digital computer consisting of digital circuits are available engineers were looking for an appropriate form to describe such digital circuits by means of computers. The aim was to simulate circuits and to test their function before the circuits were transferred into hardware. Such form is, for example, HDL (Hardware Description Language). The latest step in this respect is the development of VHDL (Very high speed integrated circuits Hardware Description Language). VHDL was standardized in IEEE 1076 in 1987, extended in 1993 (IEEE 1164), and further extended in 1999 in IEEE 1076.1, also known as VHDL-AMS (Analog and Mixed Signals). VHDL can be used for documentation, verification, and synthesis of large digital hardware designs. This is actually one of the key features of VHDL, since the same VHDL code can achieve all three of these goals, thus saving a lot of effort and reducing the introduction of errors between translating a specification into an implementation.
Usually a VHDL-Model consists of three parts: an entity, an architecture, and one or more configurations. Sometimes also packages are used and test benches must be written to test models.
An entity declaration in VHDL is a statement that defines the external specification of a circuit or sub-circuit. Using the information provided in an entity declaration (the port names and the data type and direction of each port), one has all the information needed to connect that portion of a circuit into other, higher-level circuits, or to design input stimulus for testing purposes. The actual operation of the circuit, however, is not included in the entity declaration.
A very simple example is a NAND gate as shown in FIG. 1. At the top of the example is a library clause (LIBRARY IEEE;) and a use clause (USE IEEE.std_logic—1164.ALL;). This gives the entity access to all names declared within package STD_LOGIC—1164 in the library IEEE. The entity declaration includes the name of the entity and a set of generic and port declarations. GENERICS are constants passed into components, usually counts or delays. The PORT statement allows to define system I/O. A port may correspond to a pin on a IC, an edge connector on a board, etc. The following are signal types which can be declared in the port statement:
INInput to the systemOUTOutput from the systemINOUTA bi-directional signalBUFFERA register attached to an output. (It is normallyimpossible to read an output, but a buffer allows this.)The generic in the shown example is defined with type time because it is a delay value of 5 ns, although it is possible to pass in any VHDL type.
The second part of a VHDL-model is the architecture declaration. Every entity declaration must be accompanied by at least one corresponding architecture in order to describe how the model operates. VHDL allows to create more than one alternate architecture for each entity. An architecture declaration consists of zero or more declarations (of items such as intermediate signals, components that will be referenced in the architecture, local functions and procedures and constants) followed by a begin statement and a series of concurrent statements. The name of the architecture body is just an arbitrary label selected by the user. Within an architecture all statements are concurrent. There are two commonly used approaches for an architecture description, structural and behavioral. FIG. 2 gives an example of how a complete system can be build hierarchically by combining structural and behavioral models.
A behavioral model is one which defines the behavior of a system, i.e., how a system acts. The used statements are PROCESS, WAIT, IF, CASE, FOR-LOOP. The NAND gate of FIG. 1 can be described in a behavioral model as follows:
architecture behavior of NAND isbeginc <= NOT (a AND b) after DELAY;end behavior;
The architecture contains a concurrent signal assignment which describes the function of the design entity. The concurrent assignment executes, whenever one of the ports a or b changes its value. The order in which concurrent signals are written has no effect on their execution. The signal assignment from the example has a delay, that means that the signal on the left hand side is updated after the given delay.
As already mentioned, a structural model can be many levels deep, starting with primitive gates and building to describe a complete system. A RS-FlipFlop can be constructed from the simple NAND gate above, as can be seen in FIG. 3.
The FlipFlop is defined as two interconnected NAND instantiations. These are defined in separate VHDL code. This allows to use different levels in coding. For example, it would be possible to instantiate the RS-FF component to form a shift register. It is necessary that the ports in a component declaration match the ports in the entity declaration one for one. The names, order, mode and types of the ports to be used are defined in the component declaration. A component has to be declared only once within an architecture, but may be instanced several times (two times in this example).
In this example the component NAND has two inputs (a and b) and an output (c). There are two instances of the NAND component in this architecture. The first line of the component instantiation statement gives this instance a name, nand1, and specifies that it is an instance of the component NAND. The second line describes how the component is connected to the rest of the design using the port map clause. The port map clause specifies what signals of the design to connect to the interface of the component in the same order as they are listed in the component declaration. The interface is specified in order as a, b, and then c, so this instance connects r to a, qb to b, and q to c. The second instance, named nand2, connects q to a, s to b, and qb to c of a different instance of the same NAND component.
The next type of design unit available in VHDL is called a configuration declaration. A configuration can be thought of as being roughly analogous to a parts list for a design. It specifies which architectures are to be bound to which entities. This allows to have different architectures bound to an entity statement and to change how components are connected in a design description at the time of simulation or synthesis. Configurations are optional, the VHDL standard specifies a set of rules that provides a default configuration, e.g. if more than one architecture for an entity is provided, the last architecture compiled will take precedence and will be bound to the entity.
A so-called package is used to collect commonly used declarations for use globally among different design units. It is identified by the PACKAGE keyword and can consist of two parts, a package declaration and an optional package body. Packages allow convenient ways of defining functions and constants which are used in more than one VHDL programs. They can be thought of as being a common storage area. Items defined within a package can be made visible to any other design unit in the complete VHDL design. They also can be compiled into libraries for later use.
Packages act like an entity, i.e., they declare the interfaces to the functions and sub-programs found in the package body. Packages defining one or more deferred constants or containing declarations of sub-programs additionally require a package body. The relationship between a package and package body is similar to the relationship between an entity and its architecture. Like an architecture a package body must have the same name as its corresponding package declaration.
When modeling a circuit design, usually pre-designed models, for example VHDL models, available on the market are used (for example models for Fast Fourier Transform, Fast Cosine Transform etc.). These models are however predefined. This is to some extent disadvantageous as it is required that some characteristics can be flexibly configured, i.e., having variable parameters. The problem here is that a hardware description language project Jill (e.g., VHDL-project) contains hardly configurable modules, for example:
GENERIC (width)IF in_adr = “XX . . . X” THENout_d <= “XXXXXXX . . . XXX”; -- cos(2*Pi*I), I=0 . . . n--<--- width --->ELSIF in_adr = “XX . . . X” THEN. . .END IF;. . .There is thus a demand that modules are configurable or flexible, such as models of CPUs or FFTs (Fast Fourier Transform).
FIG. 4 shows two conventional methods, i.e., “standard solution 1” and “standard solution 2” for providing such a flexibility in configuration. Both standard ways of VHDL project configuration require some external generation program (for example C) that creates a data file or directly a VHDL file. The standard of VHDL includes native configuration facilities expressed via “GENERIC”, “GENERATE” and “AGGREGATE” directives but these do not satisfy all configuration needs: most sophisticated parts of VHDL code are to be configured via external software that prepares text files to be imported into VHDL source through the “textio” package. This is inconvenient and inefficient.